cPCI-9116®/cPCI-9116R® 64 Ch, 16 bit, 250KS/s Analog input Card For 3U CompactPCI User’s Guide
Introduction • 1 1 Introduction The 9116 series products are advanced data acquisition cards based on the 32-bit CompactPCI architecture. The 9116 se
2 • Introduction • Five A/D trigger modes: software trigger, pre-trigger, post-trigger, middle-trigger and delay-trigger • Software Polling, Interr
Introduction • 3 1.3 Specifications ♦ Analog Input (A/D) • Converter: LT1606 (or equivalent) 250KHz • Number of channels: (programmable) P 64 si
4 • Introduction • Trigger Mode: P Software-trigger. P Pre-trigger. P Post-trigger. P Middle-Trigger. P Delay Trigger • Data Transfer: P P
Introduction • 5 P +5V @ 560mA typical P +3.3V@ 100mA typical • ±15V (pin35, pin85) Output Current (max): 5mA • +5V(pin49, pin99) Output Current
6 • Introduction 1.4.2 PCIS-LVIEW: LabVIEW® Driver PCIS-LVIEW contains the VIs, which are used to interface with NI’s LabVIEW® software package. The
Installation • 7 2 Installation This chapter describes how to install the 9116 series cards. The contents of the package and unpacking information th
8 • Installation 2.2 Unpacking The card contains electro-static sensitive components that can be easily be damaged by static electricity. Therefore,
Installation • 9 2.3 cPCI-9116 and cPCI-9116R Layout Figure 1: PCB Layout of the cPCI-9116
10 • Installation Figure 2: PCB Layout of cPCI-9116R and Rear I/O adaptor
Installation • 11 2.4 PCI Configuration 1. Plug and Play: As a plug and play component, the board requests an interrupt number via a system call.
12 • Signal Connections 3 Signal Connections This chapter describes the connectors of the 9116 series. The signal connections between the 9116 seri
Signal Connections • 13 J1 100-pin SCSI-type connector U_CMMD 1 51 AGND AIH0 AI0 2 52 AI32 AIL0 AIH1 AI1 3 53 AI33 AIL1 AIH2 AI2 4
14 • Signal Connections Legend of J1: Signal Name Definition U_CMMD User Common Mode AIn Analog Input Channel n (single-ended) AIHn Analog High
Signal Connections • 15 3.2 Analog Input Signal Connection The 9116 series provides up to 64 single-ended or 32 differential analog input channels.
16 • Signal Connections Differential input mode The differential input mode provides two inputs that respond to signal voltage differences between t
Signal Connections • 17 User Common Mode (U_CMMD) To measure ground-referenced signal sources, which are connected to the same ground point, you can
18 • Registers 4 Registers The descriptions of the registers and structure of the PCI-9116 are outlined in this chapter. The information in this ch
Registers • 19 I/O Address Read Write Base + 0x00 Scan Interval Counter Scan Interval Counter Base + 0x04 Sample Interval Counter Sample Inter
Copyright 2002 ADLINK Technology Inc. All Rights Reserved. Manual Rev. 1.02: JUL 23, 2002 Part No: 50-15002-100 The information in this document is
20 • Registers 4.2 Internal Timer/Counter Register The 9116 series card basically has 6 counters, which are responsible for the scan timing of the
Registers • 21 4.3 General Purpose Timer/Counter Register One 16-bit, general-purpose timer/counter exists in the 9116 series card. Writing to this
22 • Registers 4.4 General Purpose Timer/Counter Control Register Address: BASE + 0x20 Attribute: write only Data Format: Bit 7 6 5 4 3 2 1
Registers • 23 Clk_src (bit3): GPTC0’s clock source 1: External Input (Pin 96) 0: Internal Timebase MODE1~MODE0 (bit1 ~ bit0): GPTC0’s Mode s
24 • Registers 4.6 Channel Gain Queue Register This register is used to fill the Channel Gain Queue. We recommend users use our call function to av
Registers • 25 HL_sel(bit3): >31 channel selection (single ended) 1: when channel number is larger than 31 0: when channel number is smaller tha
26 • Registers DMA (Bit8): Write Only, set for DMA transfer SC_dis (Bit7): Write Only, set to disable the SC counter Clear Channel Gain Queue (Bit6
Registers • 27 4.8 A/D & FIFO Status Register Address: BASE + 28 Attribute: read Data Format: Bit 7 6 5 4 3 2 1 0 ACQ Full HFull Em
28 • Registers SC_TC(Bit2) : Read/ Write 1 to clear Scan Counter Terminal Count Status 1: Scan Counter counts to 0 0: Scan Counter not completed ADO
Registers • 29 Address: BASE + 30 Attribute: write Data Format: Bit 7 6 5 4 3 2 1 0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Bit 15 14 13
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30 • Registers softconv (bit10): ADC direct conversion control 1: generate 1 convert pulse 0: no effect ACQ_EN (bit9): Acquisition enable bit 1:
Registers • 31 4.11 Interrupt Control Register Address: BASE + 0x38 Attribute: write Data Format: Bit 7 6 5 4 3 2 1 0 --- --- --- Clr_T
32 • Registers EOC_en (bit8): End of conversion Interrupt Enable Control 1: Enable 0: Disable Clr_Timer (bit4): write 1 to clear the GPTC Interrupt
Registers • 33 4.12 Interrupt Status Register Address: BASE + 0x38 Attribute: read Data Format: Bit 7 6 5 4 3 2 1 0 --- --- --- Timer
34 • Operation Theory 5 Operation Theory The operation theory of the functions on the 9116 series is described in this chapter. The functions includ
Operation Theory • 35 5.1.2 Software conversion with polling data transfer acquisition mode (Software Polling) This is the easiest way to acquire a
36 • Operation Theory 5.1.2.1 Specifying Channels, Gains, and input configurations in the Channel Gain Queue In both Software Polling and programmab
Operation Theory • 37 Timebase clock source In scan acquisition mode, all the A/D conversions start on the output of counters, which use Timebase as
38 • Operation Theory Note: 1.The maximum A/D sampling rate is 250kHz. Therefore, SI2_counter can’t be smaller than 96 while using the internal Timeb
Operation Theory • 39 Then Acquisition sequence of channels: 1, 2, 0, 2, 1, 2, 0, 2, 1, 2, 0, 2. Sampling Interval = 240/24M s = 10 us Scan Interval
Table of Contents • i Table of Contents Tables ...iii Figures ...
40 • Operation Theory Acquisition_in_progress Scan_start AD_conversion Scan_in_progress (SSH_OUT)(pin47) (M_counter = M = 3, DIV_counter=4, SC_co
Operation Theory • 41 When an external trigger signal occurs before the first M scans of data are converted, the amount of stored data could be fewer
42 • Operation Theory Acquisition_in_progress Scan_start AD_conversion Scan_in_progress (SSH_OUT)(pin47) (M_counter = M = 3, DIV_counter=4, SC_co
Operation Theory • 43 (M_Counter=M=3, DIV_Counter=4, SC_Counter=N=1) Acquisition_in_progress Scan_start AD_conversion Scan_in_progress (SSH_OU
44 • Operation Theory (M_Counter=M=2, DIV_Counter=4, SC_Counter=N=2) Acquisition_in_progress Scan_start AD_conversion Scan_in_progress (SSH_OU
Operation Theory • 45 Delay Trigger Acquisition Use delay trigger acquisition in applications where you want to delay the data collection after the o
46 • Operation Theory Post-Trigger or Delay-trigger Acquisition with re-trigger Use post-trigger or delay-trigger acquisition with re-trigger functio
Operation Theory • 47 5.1.4 A/D Data Transfer Modes After the end of the A/D conversion, A/D data are buffered into the Data FIFO memory. The FIFO
48 • Operation Theory DMA Transfer PCI bus-mastering DMA is necessary for high speed DAQ in order to utilize the maximum PCI bandwidth. The bus -ma
Operation Theory • 49 5.3 General Purpose Timer/Counter Operation An independent 16-bit up/down timer/counter is designed in the FPGA for user appli
ii • Table of Contents 4.6 Channel Gain Queue Register ... 24 4.7 A/D & FIFO Control Register...
50 • Operation Theory • Two programmable timer modes are provided: Mode 0: Interrupt on Terminal Count Mode 0 is typically used for event counting,
Software Utility & Calibration • 51 6 Software Utility & Calibration This software CD provides a utility program, 9116util.exe, and is intend
52 • Software Utility & Calibration ****** cPCI-9116 Utility Rev. 1.0 ****** Copyright © 2001-2002, ADLINK Technology Inc. All rights reserved
Software Utility & Calibration • 53 6.2.2 VR Assignment There are 4 variable resistors (VR) on the 9116 series board that allows you to make adj
54 • Software Utility & Calibration 6.2.3.1 PGA offset Calibration 1. Short the A/D channel 0 (pin 2 of J1) to ground (pin51 of J1). 2. Use mu
Software Utility & Calibration • 55 ****** cPCI-9116 Function Testing ****** <0> : DI/DO Test <1> : A/D with Polling Test (ch0~31) &
56 • Warranty Policy Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, pleas
Warranty Policy • 57 4. Customers are responsible for the fees regarding transportation of damaged products to our company or to the sales office.
Tables • iii Tables Table 1. Legend of J1 Connector ... 14 Table 2. I/O Port Address...
iv • Figures Figures Figure 1: PCB Layout of the cPCI-9116...9 Figure 2: PCB Layout of cPCI-9116R and Rear I/O adap
How to Use This Guide • v How to Use This Guide This manual is designed to help you use the 9116 series. The manual describes how to modify various s
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